(a) Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a dummy cell pattern in addition to a memory cell pattern.
(b) Description of the Related Art
A semiconductor memory device comprises a cell array area in which cell transistors are arranged in row and column directions for storing information and a plurality of associated basic patterns constituting a drive circuit including sense amplifiers and sub-word decoders.
FIG. 1 shows an example of the conventional semiconductor memory device having a cell array block of a stacked capacitor structure. The cell array block 13 comprises a memory cell section 12 in which a plurality of memory cell patterns 12a are arranged in a matrix on a semiconductor substrate and a dummy cell section 11A in which a plurality of dummy cell patterns 11b are disposed in the peripheral area surrounding the memory cell section 12 on the semiconductor substrate.
Outside the dummy cell pattern area 11A, there is provided a drive circuit section 14 in which sub-word decoders 14a are disposed in the vicinities of the top and bottom edges of the memory device and sense amplifiers 14b are disposed in the vicinities of the left and right edges of the memory device, and other driving circuits 14c disposed in the vicinity of four corners of the memory device.
FIG. 2A is a partial enlarged top plan view taken in the vicinities of line X--X in FIG. 1, and FIG. 2B is a cross-sectional view taken along line X--X for showing some mask patterns for multiple layers overlaid in photolithographic processes in the fabrication of the semiconductor memory device. In FIG. 2A, the memory device comprises diffused regions formed in a silicon substrate, word lines 16 formed as gate lines for pairs of the diffused regions 15, digit lines 17 overlying the word lines 16 and connected to one of the pairs of diffused regions 15. A contact 18 connects the other of pair of diffused regions 15 with a lower poly-Si electrode 22 of a stacked capacitor. An overall area shown in FIG. 2A or the cell array area 13 in FIG. 1 is provided with an upper poly-Si layer 20 as the other electrode for the stacked capacitor.
In FIG. 2B, the memory cell pattern section 12, the dummy cell pattern section 11A and the drive section 14 are shown by separating these regions by dotted lines.
The dummy cell pattern is provided because of the following reasons. In the photolithographic process for LSI wafer processing, an incident light to the wafer from an exposure unit and a reflected light generated from the incident light interfere each other during a photoresist exposure step. The wavelength, amplitude and cycle of both incident and reflected lights are the same but in opposite directions in these lights, thereby generating a standing wave which does not travel in any direction. The amplitude of the standing wave differs depending on the phase of the incident light at the reflection point, and assumes at a maximum 2 times the incident wave. In such an area where the standing wave exists, the shape of pattern transferred on the photoresist layer suffers from an adverse effect. Particularly, its effect is larger for the stacked poly-Si pattern without a dummy cell pattern because the cell pattern has a smaller dimension at an array edge of the memory pattern area 12 due to the following reason.
The memory cell pattern area 12 has a high density in lower conductive layers. Due to this reason, the surface is normally raised higher in the cell pattern area 12 than in the sub-word decoder 14a and the sense amplifiers 14b disposed in the peripheral area. The structure of the stacked poly-Si layer 22 and the capacitor poly-Si layer 20 disposed above the memory cell pattern area 12 causes a large thickness difference between the memory pattern area 12 and the drive circuit area 14.
FIG. 3A is a cross-sectional view of a semiconductor memory device without having the dummy cell pattern during an exposure step in a stacked poly-Si pattern fabrication process thereto. The cell array area 13 consists of the memory cell pattern area 12, and the cell drive circuit 14 is disposed in the outer peripheral area. A stacked poly-Si layer 22 and a photoresist layer 24 are formed on the entire surface of the underlying structure formed on a wafer 25. A reticle 23 is attached on an exposure unit to transfer a desired poly-Si pattern on the photoresist 24. Here, an incident light from the exposure unit to the cell array peripheral area 12c is denoted by 27 and an incident light to the central cell array area is denoted by 28. A photoresist area 24 is exposed and removed after development if a positive type photoresist is used in the area where a light is exposed. Other area masked with chrome etc. is left as a necessary pattern.
In FIG. 3A, the stacked poly-Si pattern at the cell array peripheral area 12c is denoted by 30 and the stacked poly-Si pattern in the cell array central area 12d is denoted by 31. The surface of cell array peripheral area 12c is disposed lower than the surface of the cell array central area 12d by a gap of "h". Usually, in this condition, the stacked poly-Si pattern 30 at the cell array peripheral area 12c becomes thinner than the stacked poly-Si pattern 21 in the central area 12d.
Referring to FIG. 3B showing waveforms of the light incident to the memory device, i1 denotes the light incident to the cell array peripheral area 12c and j1 the light incident to the cell array central area 12c Both i1 and j1 travel with their respective amplitudes B, cycles T and wavelengths .lambda. to arrive at respective reflecting points. Y axis or horizontal direction in the drawing denotes displacement during the travel, and X axis or vertical direction in the drawing denotes wavelengths of the lights. The reflecting point where the wave i1 incident to the cell array edge area is denoted as "k", the reflecting point where the wave j1 incident to the cell array central area is denoted by "m". The location of the reflection point "m", at the cell array central area 12d is raised by a difference "h" from the reflecting point "k" at the cell array peripheral area 12c.
There is no displacement of the incident wave j1 at the reflecting point "m", whereas a displacement of the incident wave i1 at the reflecting point "k" is -B. The phase of i1 is 5/4.lambda. deviated from the phase of the incident wave j1 at the reflecting point "m". As a result, a complex wave or standing wave at the respective reflecting points of incident wave i1 and incident wave j1 show different phases.
Here, reflected wave generated from the incident wave i1 at the reflecting point "k" is denoted by i2, and reflected wave generated from the incident wave i1 at the reflecting point "m" is denoted by j2. The waveform of the reflected wave i2 overlaps with the waveform of the incident wave i1 and the waveform of the reflected wave j2 shifts by .lambda./2 in phase from the incident wave j1. The composite wave made from the incident wave i1 and the reflected wave i2 assumes waveform I which has a displacement of 2B or 2 times that of the incident wave i1 at the cell array peripheral area 12c. The composite wave made from the incident wave j1 and the reflected wave j2 assumes waveform J which is of a straight line after the incident wave j1 and the reflected wave j2 are cancelled by each other at the cell array central area 12c. As a result, the cell array central area 12d is less influenced than the cell array peripheral area.
If the driving circuit block 14 is in direct contact with the memory cell section 12 (in this case, it equals to the cell array block 13), it results in the reduction of the dimension of the cell pattern at the cell array peripheral area 12c, causing a storage failure or loss of information stored. In FIG. 1, the dummy cell pattern area 11A disposed at the outer periphery of the cell array area is provided for prevention of the deterioration of the stacked poly-Si transfer accuracy caused by the standing wave at the memory pattern peripheral area 12.
In a conventional semiconductor memory device having the dummy pattern area disposed on outer periphery of the memory pattern area 12, the dummy cell area is generally designed so that it does not protrude into the drive circuit area 14 disposed on the further outer area in which the sub-word decoder 14a, the sense amplifier 14b and their drive circuit 14c are provided.
FIG. 3C is a cross-sectional view in an exposure process in the fabrication of stacked poly-Si pattern for the semiconductor memory device having the dummy cell pattern area 11A for the improvement of photoresist transfer accuracy. The dummy cell pattern area 11A is provided in the outer peripheral area 12c of the memory cell pattern area 12. The incident wave 29 is irradiated on the dummy pattern area 11A in which the dummy cell pattern 11b is disposed. There step-difference "h" is removed between the array central area 12d and the array edge area 12c by the deposition of the dummy cell pattern 11b in the memory pattern area 12. As a result, smaller dimension of the cell pattern is prevented which is generally caused by the standing wave due to the wave 27 incident to the stacked poly-Si pattern 20 in the array peripheral area 12.
The cell array area 13 in FIG. 3C, comprising the memory cell section 12, the dummy cell section 11A surrounding the memory cell section 12 and the cell drive circuit 14 disposed outside the dummy cell section. Inaccurate pattern transfer of the photoresist due to the standing wave is prevented during the fabrication of stacked poly-Si pattern at the peripheral area 12c of the cell array 13 in a conventional method by adding the dummy cell pattern area 11A. The structure, however, involves a smaller dimension of the memory device.